1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming a circuit that includes a cross-coupling gate contact structure wherein the circuit is to be manufactured using a triple patterning process.
2. Description of the Related Art
Photolithography is one of the basic processes used in manufacturing integrated circuit products. At a very high level, photolithography involves: (1) forming a layer of light or radiation-sensitive material, such as photoresist, above a layer of material or a substrate; (2) selectively exposing the radiation-sensitive material to a light generated by a light source (such as a DUV or EUV source) to transfer a pattern defined by a mask or reticle (interchangeable terms as used herein) to the radiation-sensitive material; and (3) developing the exposed layer of radiation-sensitive material to define a patterned mask layer. Various process operations, such as etching or ion implantation processes, may then be performed on the underlying layer of material or substrate through the patterned mask layer.
Of course, the ultimate goal in integrated circuit fabrication is to faithfully reproduce the original circuit design on the integrated circuit product. Historically, the feature sizes and pitches (spacing between features) employed in integrated circuit products were such that a desired pattern could be formed using a single patterned photoresist masking layer. However, in recent years, device dimensions and pitches have been reduced to the point where existing photolithography tools, e.g., 193 nm wavelength photolithography tools, cannot form a single patterned mask layer with all of the features of the overall target pattern.
Accordingly, device designers have resorted to techniques that involve performing multiple exposures to define a single target pattern in a layer of material. One such technique is generally referred to as double patterning. In general, double patterning is an exposure method that involves splitting (i.e., dividing or separating) a dense overall target circuit pattern into two separate, less-dense patterns. The simplified, less-dense patterns are then printed separately on a wafer utilizing two separate masks (where one of the masks is utilized to image one of the less-dense patterns, and the other mask is utilized to image the other less-dense pattern). Further, in some cases, the second pattern is printed in between the lines of the first pattern such that the imaged wafer has, for example, a feature pitch which is half that found on either of the two less-dense masks. This technique effectively lowers the complexity of the photolithography process, improving the achievable resolution and enabling the printing of far smaller features that would otherwise be impossible using existing photolithography tools. One well-known double patterning technique is referred to as LELE (“litho-etch-litho-etch”) double patterning. As the name implies, the LELE process involves forming two photoresist etch masks and performing two etching processes to transfer the desired overall pattern to a hard mask layer that is then used as an etch mask to etch an underlying layer of material.
Double patterning techniques have been successfully employed in manufacturing integrated circuits using 20 nm and 14 nm technology. However, as device dimensions continue to shrink and packing densities continue to increase, for example, in 10 nm technology (and beyond) based integrated circuit products, double patterning techniques are insufficient to form at least some of the features in such products. Accordingly, mask designers have begun using so-called triple patterning techniques to form the circuits on such advanced integrated circuit products. As its name implies, triple patterning is an exposure method that involves separating a dense overall target circuit pattern into three separate, less-dense patterns. Each of the three simplified, less-dense patterns are then printed separately on a wafer utilizing three separate masks or reticles. One well-known triple patterning technique is referred to as LELELE (“litho-etch-litho-etch-litho-etch”) triple patterning. As the name implies, the LELELE triple patterning process involves forming three photoresist etch masks and performing three etching processes to transfer the desired overall pattern to a hard mask layer that is then used as an etch mask to etch an underlying layer of material.
Cross-coupling gate contact structures are important for standard cell design to achieve product area scaling goals of advanced technology nodes. Such cross-coupling gate contact structures may be employed in a variety of common circuits, e.g., flip-flops, MUX, etc. FIG. 1A depicts a simplified example of a prior art circuit 10 employing such a cross-coupling gate contact structure 20. In general, the circuit 10 is comprised of a plurality of transistor structures that are formed in and above spaced-apart regions 12 of a semiconductor substrate that are separated by isolation material, e.g., silicon dioxide. The circuit 10 further includes a plurality of gate structures 14, source/drain regions 16, source/drain contact structures 18 and an illustrative cross-coupling gate contact structure 20. The source/drain contact structures 18 and the cross-coupling gate contact structure 20 are formed after the gate structures 14 and the source/drain regions 16 are formed. In general, the source/drain contact structures 18 and the cross-coupling gate contact structure 20 are formed at the device contact level, i.e., at a level below the so-called via zero (V0) that is formed to establish electrical contact between the device level contacts and the first general metal layer (so-called M1 layer) that is the first general wiring layer for the integrated circuit product. In the embodiment shown in FIG. 1A, the cross-coupling gate contact structure 20 is formed at an angle of about 45° relative to the long axis of the gate structures 14. FIG. 1B depicts an alternative example of a cross-coupling gate contact structure 20A that has a portion that is positioned approximately at right angles to the long axis of the two connected gate structures 14. In some integration schemes, the cross-coupling gate contact structure 20 connects the gate through another contact structure that is called a gate contact and not shown in the simplified schematic as shown in FIG. 1A. Other configurations of such cross-coupling gate contact structures are also possible.
The use of such cross-coupling gate contact structures is highly desirable because it enables a reduction in cell area and it reduces manufacturing complexities. Absent the use of such cross-coupling gate contact structures, the electrical connections to the connected gate structures would have to be made using features formed in the V0 and M1 layers, which would thereby complicate the manufacturing of those features and increase the already tight spacing that exists in the V0/M1 layers.
As noted above, the integrated circuit design is eventually fabricated by transferring the circuit layout to a semiconductor substrate in a series of layers that collectively will form the features that constitute the devices that make up the components of the integrated circuit. However, before the layout can be fabricated, a validation process of the layout must take place. Layout designers use very sophisticated Electronic Design Automation (EDA) tools and programs when designing circuit layouts for modern integrated circuit products. As it relates to triple patterning techniques, an overall target pattern must be what is referred to as triple-patterning-compliant. In general, this means that an overall target pattern is capable of being decomposed into three separate patterns that each may be printed in a single layer using existing photolithography tools. Layout designers sometimes speak of such patterns with reference to “colors,” wherein the first mask will be represented in the EDA tool using a first color, the second mask will be represented in the EDA tool using a second, different color, and the third mask will be represented in the EDA tool using a third color that is different from the colors used to represent the first and second masks. To the extent a layout is non-triple-patterning-compliant, it is sometimes stated to present a “coloring conflict” between the conflicting masks.
Unfortunately, in 10 nm technology and below, cross-coupling gate contact structures, such as those depicted in FIG. 1A, that are assigned to a single mask cannot be made using traditional triple patterning techniques because of coloring conflict rules. FIG. 1C depicts one illustrative example of possible color assignment of the source/drain contact structures 18 (18A-J) and the cross-coupling gate contact structure 20 to masks 1-3 in an attempt to form the circuit 10 using triple patterning techniques. As depicted therein, the source/drain contact structures 18A, 18C, 18E, 18F, 18H and 18J and the cross-coupling gate contact structure 20 are assigned to Mask 1. The source/drain contact structures 18G and 18I are assigned to Mask 2. The source/drain contact structures 18B and 18D are assigned to Mask 3. The coloring assignment depicted in FIG. 1C cannot be formed using triple patterning techniques because the spacing 17 between the cross-coupling gate contact structure 20 and the nearest source/drain contact structures, e.g., the features 18C and 18H, all three of which are formed on Mask 1, violate the minimum spacing rules for Mask 1. If such cross-coupling gate contact structures cannot be used in future integrated circuit products that are required to be formed using triple-patterning techniques, then there will be an undesirable increase in the plot space consumed by such circuits and manufacturing such circuits will become more complex.
The present disclosure is directed to various methods of forming a circuit that includes a cross-coupling gate contact structure wherein the circuit is to be manufactured using a triple patterning process which may solve or at least reduce one or more of the problems identified above.